Dynamic random access memory (DRAM) devices are used extensively in the electronics industry for information storage. A high density DRAM includes millions of memory cells. Each memory cell on the DRAM chip comprises a pass transistor, e.g. a metal-oxide-semiconductor field-effect transistor (MOSFET) and a storage capacitor for storing charge. Embedded DRAM (EDRAM) is a type of integrated circuit (IC) that combines DRAM circuits and logic circuits together in a semiconductor substrate. Nowadays, the trend in manufacturing semiconductor ICs is to integrate memory cell arrays with high-speed logic circuit elements. For example, microprocessors or digital signal processors all have integrated circuits that incorporate embedded memory.
However, the prior method of fabricating EDRAM encounters a serious topographical problem of an interlayer dielectric (ILD) layer before a metallization process is carried out. More specifically, the prior method encounters a problem resulting from a large difference in height on the ILD layer between a memory region and a logic region on an EDRAM. The problem of this large step height difference becomes increasingly critical for the production yield. With large step height difference, severe defects such as routing failure occur in the subsequent metallization process.